1. Field
Exemplary embodiments of the present invention relate to an operating method of a nonvolatile memory device, and more particularly, to a programming method of a nonvolatile memory device.
2. Description of the Conventional Art
Recently, the demand for nonvolatile memory devices which can be electrically programmed and erased and can maintain data even in a state where power is not supplied has rapidly increased. Among the nonvolatile memory devices, a NAND flash memory device includes a plurality of memory cells connected in series such that adjacent cells share a drain or source, and forming one string. Therefore, the NAND flash memory device is suitable for storing large information.
Specifically, a string forming a NAND flash memory device includes a drain select transistor, a plurality of memory cells, and a source select transistor, which are connected in series between a bit line and a common source line. The drain select transistor, the memory cells, and the source select transistor have gates connected to a drain select line, word lines, and a source select line, and controlled by the drain select line, the word lines, and the source select line, respectively A plurality of strings and a plurality of bit lines connected to the respective strings form a memory cell block.
In order to program memory cells, an erase operation is performed on the memory cells such that the memory cells have a negative threshold voltage. Then, a high voltage as a program voltage is applied to a word line of a memory cell selected for programming such that the selected memory cell has a higher threshold voltage. At this time, the threshold voltages of the other unselected memory cells must not be changed.
During the program operation, however, a program voltage is applied to not only the selected memory cell, but also an unselected memory cell sharing a word line with the selected memory cell. Therefore, program disturbance may occur, in which the unselected memory cell connected to the selected word line is programmed. Conventionally, in order to prevent the program disturbance, the following method has been used: a drain select transistor and a source select transistor of an unselected string are turned off to float a channel of the memory cells of the unselected string, and a program voltage and a pass voltage are applied to a selected word line and an unselected word line to boost the channel voltage of the memory cells of the unselected string.
However, the conventional channel boosting method may not acquire a program disturbance prevention effect depending on the position of the selected memory cell. Specifically, when the selected memory cell is positioned at an end portion in the extension direction of the string, the program disturbance prevention effect may decrease. Hereafter, referring to FIGS. 1A and 1B, such a problem will be described in more detail.
FIGS. 1A and 1B are diagrams for explaining the problem of the conventional method. In particular, FIG. 1A is a cross-sectional view of an unselected string when a selected memory cell is the most adjacent to a common source line CSL, and FIG. 1B is a cross-sectional view of an unselected string when a selected memory cell is the most adjacent to a bit line BL.
Referring to FIG. 1A, a power supply voltage Vcc is applied to a common source line CSL, a drain select line DSL, and a bit line BL of an unselected string, and 0V is applied to a source select line SSL, thereby floating a channel of memory cells of the unselected string.
Subsequently, when a program voltage Vpgm is applied to a word line WL0 of the selected memory cell and a pass voltage Vpass is applied to the other word lines WL1 to WLn, channel voltages of the memory cells are boosted. At this time, since the program voltage Vpgm is higher than the pass voltage Vpass, the channel voltage CH1 boosted under the word line WL0 is larger than the channel voltages CH2 boosted under the other word lines WL1 to WLn.
In this case, since a difference between the channel voltage under the word line WL0 and the voltage Vcc applied to the adjacent common source line CSL is large, a leakage current may flow to the common source line CSL (refer to {circle around (1)}). Accordingly, the channel voltage under the word line WL0 decreases. That is, since the boosting degree of the channel voltage of the memory cell connected to the word line WL0 in the unselected string cannot be maintained, the corresponding memory cell may be programmed.
Furthermore, referring to FIG. 1B, a channel of memory cells of an unselected string is floated in the same manner as FIG. 1A.
Then, when a program voltage Vpgm is applied to a word line WLn of a selected memory cell and a pass voltage Vpass is applied to the other word lines WL0 to WLn−1 channel voltages of the memory cells are boosted. At this time, the channel voltage CH1 boosted under the word line WLn is higher than the channel voltages CH2 boosted under the other word lines WL0 to WLn−1.
In this case, since a difference between the channel voltage under the word line WLn and a voltage Vcc applied to an adjacent bit line BL is large, a leakage current may flow to the bit line BL (refer to {circle around (2)}). Accordingly, the channel voltage under the word line WLn decreases. That is, since the boosting degree of the channel voltage of the memory cell connected to the word line WLn in the unselected string cannot be maintained, the corresponding memory cell may be programmed.